The present invention generally relates to an optical transmission system, and particularly to a phase synchronism circuit for use in optical fiber transmission.
In the optical transmission system, a photodetector photoelectrically converts a received optical signal to an electrical signal. The NRZ coded binary data produced after this converted electrical signal is equalized, amplified and digitized has small jitter when the received optical level is large, but increases the jitter as the received optical level decreases. When no optical signal is detected, noise output is produced which corresponds to infinite jitter. In addition, a pulse width distortion is caused in this data by optical transmission and receiving circuits.
FIG. 1 shows the construction of a related phase frequency synchronism circuit that generates from such data signal a clock signal synchronized with that data. Referring to FIG. 1, there is shown a phase comparator 10 that generates a pulse voltage of a peak value or pulse width corresponding to the phase difference between the input data and the clock signal. A frequency comparator 20 produces the difference of the frequency of the clock signal to the transmission rate of the input data. When the input data and the clock signal are synchronized to within a predetermined phase difference, no frequency difference is produced. The output from the phase comparator 10 and the output from the frequency comparator 20 are supplied through an overlap unit 80 to a loop filter 40. A VCO (voltage controlled oscillator, hereinafter referred to as VCO) 50 generates the clock signal with the oscillation frequency changed on the basis of the output from the loop filter 40, and feeds it back in order that the input data and the clock signal can be synchronized with each other. The phase frequency synchronism circuit of this construction is described in, for example, xe2x80x9cTP10.3:A 8 Gb/s Si Bipolar Phase and Frequency Detector IC for Clock Extractionxe2x80x9d, 1992 IEEE International Solid-State Circuits Conference, p. 162, and JP-A-6-216766.
A storaging apparatus using disks has vibration of about 1% of the data rate because of irregular rotation of disks. As compared with the data signal from the optical receiver, the data signal from the filing apparatus has small jitter and pulse width distortion. FIG. 2 shows the construction of a related phase frequency synchronism circuit that generates from the data signal a clock signal synchronized with that data. Referring to FIG. 2, there is shown a first phase comparator 10-1 that generates a pulse voltage of a pulse with corresponding to the phase difference between the input data and the clock signal. A rate (frequency) comparator 600 compares the input data and the clock signal to detect if the clock signal exceeds a specified limit of the mark length of the data, and produces the decision output of if the bit rate (frequency) of the clock is higher or lower than that of the data.
A second phase comparator 10-2 generates a pulse voltage of a pulse width corresponding to the leading or lagging phase difference between the input data and the clock signal. The second phase comparator 10-2 receives the input data, the clock signal and the output from the rate comparator 600 and generates the pulse voltage of the pulse width corresponding to either leading or lagging phase difference between the input data and the clock signal according to the output from the rate comparator 600. A synchronous identifying unit 30 compares the input data and the clock signal to detect if the clock signal exceeds a specified limit of the mark length of the data, thus deciding if the input data and the clock signal are synchronized. A switch 1 is provided between the output of the first phase comparator 10-1 and a first loop filter 40-1 and operated to close or open when the synchronous identifying unit 30 decides that those signals are synchronized or not synchronized, respectively. A switch 2 is placed between the output of the second phase comparator 10-2 and a second loop filter 40-2 and operated to open or close when the synchronous identifying unit 30 decides that those signals are synchronized or not synchronized, respectively. The outputs from the first and second loop filters 40-1, 40-2 are supplied through an adder 90 to the VCO 50. The VCO 50 produces the clock signal with its oscillation frequency changed in accordance with the output from the adder 90, and feeds it back in order that the input data and the clock signal can be synchronized. The phase frequency synchronism circuit of this construction is described in JP-A-9-284269.
In the phase frequency synchronism circuit shown in FIG. 1, the loop filter constant is determined by the characteristic of the loop of the phase comparator 10, loop filter 40 and VCO 50 when the input data and the clock signal are synchronized. A loop of the frequency comparator 20, loop filter 40 and VCO 50 is used when the input data and the clock are not synchronized. Since the loop filter constant for the asynchronous state cannot be selected, there is a problem that it takes a long time to reach the synchronous state from the asynchronous state.
Let us consider that in the phase frequency synchronism circuit shown in FIG. 2, the frequencies of the input data and clock signal become close to each other from the asynchronous state in which the switches 1 and 2 are respectively opened and closed, resulting in the generation of a xe2x80x9csynchronousxe2x80x9d deciding signal from the synchronous identifying unit 30. The generation of the xe2x80x9csynchronousxe2x80x9d deciding signal means that the output from the adder 90, or the sum of the output from the first loop filter 40-1 and the output from the second loop filter 40-2 approaches a predetermined value relative to the oscillation frequency of the VCO 50. It is supposed from this situation that there is a voltage level difference between the output from the first phase comparator 10-1 and the output from the first loop filter 40-1. When the switches 1 and 2 are closed and opened, respectively, there is a possibility that the output from the adder 90 suddenly changes due to the voltage level difference between the output of the first phase comparator 10-1 and the output of the first loop filter 40-1, making the phase frequency synchronism circuit unstable. Therefore, although the phase frequency synchronism circuit of FIG. 2 having the two loop filters is able to separately set the frequency pull-in characteristic and phase pull-in characteristic, it may become unstable when switching is made from the frequency pull-in mode to the phase pull-in mode.
In addition, let us consider that the phase frequency synchronism circuit of FIG. 1 receives binary data with large jitter resulting from equalizing, amplifying and digitizing a faint optical signal. Even when the synchronism circuit shown in FIG. 1 achieves that the input data and the clock signal are synchronous in their phases, the input jitter may instantaneously exceed a certain phase difference to cause the frequency comparator 10 to be operative so that the clock jitter increases in an instant. In the phase frequency synchronism circuit of FIG. 2, when the input jitter instantaneously exceeds a predetermined phase difference, the synchronous identifying unit 30 may decide by mistake that the input data and the clock signal are asynchronous by mistake. As a result, switching is made from the phase synchronous mode to the frequency synchronous mode so that the clock jitter increases. If a phase frequency synchronism circuit having a characteristic to increase jitter in the clock signal is used in the optical receiver, the error rate may suddenly increase.
In addition, when the input data is generally NRZ coded and has pulse width distortion, a phase comparator that generates a voltage of a peak value or pulse width corresponding to the phase difference of the clock signal relative to both leading and trailing edges of the input data will randomly generate a pulse voltage of the different peak values or pulse widths. In the phase comparator mode loop structure formed of a phase comparator, filter and VCO, when a pulse voltage of two different peak values or pulse widths is produced randomly, the random component of the phase comparator output within the loop band causes the clock jitter to increase. In the loop structure formed of a frequency comparator, filter and VCO, when the phase comparator randomly generates a pulse voltage of two different peak values or pulse widths, the intervals at which the frequency comparing decision is made are not integral multiples as wide as the input data width, resulting in low precision with which the frequency comparing decision is made. When the frequency synchronizing mode cannot make frequency pull-in operation up to the frequency to which the phase synchronizing mode can make pull-in operation, the phase frequency synchronism circuit may make erroneous synchronization operation.
Accordingly, it is an object of the invention to provide a phase frequency synchronism circuit having a phase synchronizing loop formed of a phase comparator, filter and VCO for the synchronous state and a frequency synchronizing loop formed of a frequency comparator, filter and VCO for the asynchronous state, and capable of reducing the time taken for the input data and the clock signal to become synchronous from the asynchronous state without unstable operation when switching is made from the frequency synchronizing loop to the phase synchronizing loop.
It is another object of the invention to provide a phase frequency synchronism circuit normally capable of making synchronous operation by the phase comparison mode, and capable of preventing the clock jitter from instantaneously increasing in order that, when the input data has jitter that instantaneously exceeds a certain phase difference, a synchronous identifying unit decides that the input data and the clock are synchronous, causing the output of the frequency comparator not to be transmitted to the loop filter and the phase comparison mode to be used for the synchronizing operation even if the input jitter increases to make the frequency comparator instantaneously operative.
It is still another object of the invention to provide a phase frequency synchronism circuit capable of preventing jitter due to the random component of NRZ code when the input data is NRZ coded and has pulse width distortion, and capable of making the intervals at which the frequency comparator compares an integral multiple as wide as the width of the input data when the input data is NRZ coded and has pulse width distortion, thus preventing the precision of the frequency comparator from being reduced.
In order to solve the above problem, according to the present invention, there is provided a phase frequency synchronism circuit including a phase comparator that receives input data and a clock signal and generates a voltage of a peak value or pulse width according to the phase difference of the clock signal to the input data, a frequency comparator that receives the input data and the clock signal and generates an output resulting from deciding if the frequency of the clock signal is higher or lower than the transmission rate of the input data, a synchronous identifying unit that receives the input data and the clock signal and decides if the input signal and the clock signal are synchronized in their phases and frequencies, a switch 1 that receives the output from the phase comparator and is closed and opened when the synchronous identifying unit decides that they are synchronized and not synchronized, respectively, a switch 2 that receives the output from the frequency comparator and is opened and closed when the synchronous identifying unit decides that they are synchronized and not synchronized, respectively, a loop filter that receives the outputs from the switches 1, 2, and a voltage controlled oscillator that generates the clock signal with its frequency changed on the basis of the output from the loop filter.